網路磁帶機

這是電子鐘的程式VHDL的主程式與腳位接腳
其他子程式可以mail

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.my_pkg.all;
Entity clock is
Port(rst : in std_logic;--power reset to initialize
osc : in std_logic;--system clock
seg7 : out std_logic_vector(7 downto 0);
DE : out std_logic_vector(3 downto 1));
End clock;
architecture arch of clock is
signal Hz1,Hz64:std_logic;--1 Hz and 64 Hz clock
signal int60:integer range 0 to 59;
signal ten4,one4:std_logic_vector(3 downto 0);
signal ten8,one8:std_logic_vector(7 downto 0);
begin
u0:div10m port map(clk=>osc,f1hz=>Hz1);
u1:div64 port map(clk=>osc,f64hz=>Hz64);
u2:count60 port map(rst=>rst,carry=>hz1,times=>int60);
u3:i60bcd port map(interg=>int60,ten=>ten4,one=>one4);
u4:bin2led port map(bin=>ten4,led=>ten8);
u5:bin2led port map(bin=>one4,led=>one8);
u6:scan2 port map(rst=>rst,clk=>Hz64,a=>ten8,b=>one8,DE=>DE,mux_out=>seg7);
end arch;

rst : 54
osc : 141
seg7[7..0] : 32 31 30 29 28 27 26 23
DE[2..0] : 37 36 33